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NXP Semiconductors
SSL3250A
Photo flash dual LED driver
connected to the output stages of a device. Data transfer may only be initiated when the
bus is not busy. The SSL3250A I 2 C bus characteristic is according to the 400 kbit/s
Fast-mode I 2 C from the I 2 C-bus specification.
Remark: For more details on the I 2 C standard, refer to the document UM10204, “I 2 C-bus
specification and user manual”, version 0.3, June 2007 , which can be downloaded from
the NXP web site (www.nxp.com).
The following describes the protocols used by the SSL3250A for the read and write
sequences. The read sequence may use a repeated start condition during the sequence
to avoid that the bus is released during the communication. The sequences can be used
to read or write only one data byte or to read or write a sequence of data bytes.
Figure 12 shows a write sequence for a single byte write. Figure 13 show the read
sequence for a single byte.
S
Slave address
W
A
Sub address n
A
From master to slave
From slave to master
n th Register
S = START condition
P = STOP condition
A = Acknowledge
N = Not Acknowledged
A
P
014aaa292
Fig 12. Single byte I 2 C write sequence
S
Slave address
W
A
Sub address n
A
Sr
Slave address
R
A
n th Register
N
P
From master to slave
S = START condition
P = STOP condition
A = Acknowledge
N = Not Acknowledged
SSL3250A_5
From slave to master
Fig 13. Single byte I 2 C read sequence
Sr = Start repeat
014aaa290
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 16 December 2009
15 of 26
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